8 processor cores in one chip

CoolThreads

The above doesn't mean that Sun's good old UltaSparc architecture will be phased out any time soon. The new 64-bit UltraSparc T1, as seen in the new Sun T1000 and T2000 severs and equipped with CoolThreads technology proves that the company is still innovative, and offers features that can only be dreamt about on the X86 platform. To achieve this, Sun has had to rebuild the entire platform from scratch, and has started with a completely new design, of which the only requirement was compatibility with the earlier UltraSparc series.

This new development was sparked by discontent about the performance of the current single-threaded processors. Even though the tasks of the current network servers grow more and more multithreaded, most processors have yet to be sufficiently optimised for this. Intel had earlier tried to cope with this issue by introducing HyperThreading technology, and now it offers dual core processors, just like its rival AMD. The construction of these dual core processors is complex and this unfortunately also means a significantly higher temperature.

No baggage

But by starting from scratch, it becomes possible to change course completely. Because Sun isn't hindered by the baggage of X86 compatibility, and only has to play ball with the existing UltraSparc family and operating system, it had the opportunity to effect a big change. The advantage Sun has is that the UltraSparc architecture is a lot less complicated than X86 processors. This is the consequence of Sparc being based on a so-called RISC processor which uses a much simpler instruction set and can thus be a lot less complicated in construction.

Instead of choosing to make one or two cores as intelligent as possible (as Intel and AMD do), Sun makes do with relatively simple cores that are then used optimally. The advantage of this approach is that a more basic core requires less transistors, and that Sun can simply place more cores on the same surface. Much of the complexity in the Intel/AMD strategy lies in the prevention of idle time for the processor in which it has to wait for instructions. This includes things like long pipelines and a large cache, but also out-of-order execution and high clockspeeds. However, high clockspeeds and longer pipelines only add to the delay created by slower memory. In practice, processors end up waiting a lot for the slower memory, and are not used fully because of this.