The CPU redefined: AMD Torrenza and Intel CSI

Torrenza

AMD are the first ones to take a step in the right direction and have already announced the "Torrenza" platform last year. This technology entails that the CPU socket in a multiprocessor motherboard can also hold other types of chips. This can mean that in the future on your mortherboard you have one socket that actually holds a CPU, while the other sockets can hold co-processors that help the overall performance of the system. A GPU is the most likely candidate, but the Torrenza platform will be able to hold any kind of chip.

The technology which AMD is currently using for the Athlon 64 and Opteron processors is already well suited to for this task, meaning that AMD should be able to get Torrenza up and running in quite a short period of time. The most important factor is the HyperTransport bus that AMD implemented as a substitute for the conventional frontside bus. HyperTransport is an extremely fast interface, allowing for the efficient and rapid communication between two separate chips. In an Athlon 64 system the HyperTransport functions as nothing more than a substitute for the standard frontside bus and only really starts to show its potential when used in combination with multi-processor Opteron systems. The system used by Intel is based around one central point i.e. all the processors are connected through one or more busses to the chipset. In an Opteron multi-processor system all the processors are collectively connected through the use of separate HyperTransport connections. This means that all of the processors can communicate directly with each other without having to go through a central point and without having to involve all the processors in the system in doing so. This form of one to one communication is already being implemented to allow Opteron processors to communicate rapidly and efficiently with each other, but in the near future this technology will also allow processors and co-processors to work together, whilst keeping latencies as low as possible.

Another advantage of the AMD architecture is the integrated memory-controller within the processor, as a result of which each socket is in direct connection with its own memory, something which will also be of great benefit to co-processors. The beauty of the HyperTransport architecture lies in the fact that different chips can make use of each others memory if so required: for example when a certain chips own memory proves to be insufficient when handling a certain task or when data has to be shared collectively. In traditional system architectures the memory is controlled by the central chipset, this causes additional delays because the data has to be run through the central chipset first, this can result in the processors having to wait in line to make use of the memory

AMD's future plans

AMD is going to make use of the next generation of HyperTransport technology for the Torrenza platform, making it possible to have up to 5.2 Gigatransfers per second. So far the reactions in the market have been fairly positive with big industry names such as Dell, Cray, Fujitsu-Siemens, IBM, Sun and HP announcing their plans on implementing the Torrenza-technology in future products. Surprising is the fact that these are namely system builders and not chip manufacturers. AMD's takeover of ATI will have a positive effect on AMD's plans for Torrenza. With this takeover AMD have effectively gained all the knowledge and technology, in 3D and video applications, which ATI has to offer in one single blow. This allows AMD to produce its own co-processors for the Torrenza platform and release them onto the market. Some of the first applications for which AMD plans to implement its Torrenza technology will be for applications such as VoIP, XML and Java.

AMD has made it quite clear that it is more than willing to take this even further in future iterations of the Torrenza-technology. If certain applications prove to be exceedingly popular within the Torrenza-platform then AMD is willing to implement these directly in the CPU. Whilst 3D-chips have yet to be implemented as co-processors in a CPU-socket, AMD has already announced plans to develop processors with an integrated GPU. If implemented this technology would probably start off as two separate chips packed as one, just as current dual-core CPU's, but at a later stage could develop into true multi-functional chips